Cologne Chip - C3-PLL

<a name="top"></a> <table width="100%" > <tr> <td align=left valign="middle" width="15%"></td> <td align=left valign="middle" width="85%"> <p> <table border=0 cellspacing=0 cellpadding=0 cols=3 width="100%"> <tr> <td width="25" height="60" background="bar-left.jpg"> </td> <td height="60" background="bar-middle.jpg"><font face="Arial,Helvetica" color="#FFFFFF" size="+1">C3-PLL-2</font></td> <td width="25" height="60" background="bar-right.jpg"> </td> </tr> </table> <p> <table border="0" align="right" valign="down" cellspacing="0" rows="3" cols="3" cellpadding="5" Width=350> <tr height="25"> <td width="10" background="../../isdn/controllers/bar-upperleft.gif"> </td> <td background="../../isdn/controllers/bar-uppermiddle.gif"> </td> <td width="15" background="../../isdn/controllers/bar-upperright.gif"> </td> </tr> <tr> <td background="../../isdn/controllers/bar-leftmiddle.gif"> </td> <td align="left"><font face="Arial,Helvetica" size="-1"><b>White Papers on C3IP Technology</b> <br><br><i><a href="c3-pll-presentation_socip.pdf" target="_top">"Fully Digital Implemented Phase Locked Loop"</a></i><br>by Michael Gude & Gerriet Mueller (pdf, 34 KB)<br><br></font></td> <td background="../../isdn/controllers/bar-rightmiddle.gif"> </td> </tr> <tr height="25"> <td background="../../isdn/controllers/bar-lowerleft.gif"> </td> <td background="../../isdn/controllers/bar-lowermiddle.gif"> </td> <td background="../../isdn/controllers/bar-lowerright.gif"> </td> </tr> </table> <b>Background</b> <p> For general purpose Phase Locked Loops (PLLs), ASIC designers have to rely on analog VCOs until today. Now Cologne Chip has come up with a fully digital approach: <b>C3-PLL-2</b>, an IP core for frequency synthesizer applications. <br><br> A patent is pending for this innovation of Cologne Chip. <p> <b>Benefits</b> <p> C3-PLL-2 relies on the DIGICC design concept of Cologne Chip. This makes it possible to easily implement the core in all process technologies: C3-PLL-2 is a fully digital circuitry using standard cell libraries. Because of its pure digital nature, the PLL does neither need any additional pad or pin nor external or internal loop capacitors. On top of that, normally no external filters for the supply voltage are required. <br><br> The lock time of the PLL is very short - it is even super-fast when the PLL is restarted after stand-by mode. Furthermore the silicon space used is smaller than that of competing technologies. <br><br> More technical and commercial benefits of C3-PLL compared to conventional PLLs are listed <a href="c3-pll_benefits.pdf" target="top"><b>here</b></a> (pdf, 228 KB). <p> <b>Technical Features</b> <p> <ul type="square"> <li>Fully digital - designed for use with standard cell libraries for digital logic</li><p> <li>Implementable in any digital CMOS process technology</li><p> <li>Typical oscillator frequency ranges: <br>0.50 µm:   60-120 MHz <br>0.35 µm: 100-200 MHz <br>0.25 µm: 140-280 MHz <br>0.18 µm: 160-320 MHz <br>0.13 µm: 180-360 MHz <br>   90 nm: 200-400 MHz</li><p> <li>Frequency multiplication range: 5 to 255</li><p> <li>Predivider and post-scaler with divider range 1..256 each</li><p> <li>Jitter similar to analog PLLs</li><p> <li>No pads, special pins, external loop filter capacity or supply voltage filters needed</li><p> <li>Very fast lock time (worst case 2,000 reference clocks)</li><p> <li>Stand-by mode (oscillator stopped but center frequency adjustments preserved)</li><p> <p>> super-fast lock time when returning from stand-by mode (only some clock cycles)</li><p> <li>Stand-by also reduces power to zero (only leakage current)</li><p></p> <li>Very small area (< 3,000 gates)</li><p> </ul> <p> <p> <table border=0 cellspacing=0 cellpadding=0 cols=3 width="100%"> <tr> <td width="25" height="60" background="bar-left.jpg"> </td> <td height="60" background="bar-middle.jpg"><font face="Arial,Helvetica" color="#FFFFFF" size="+1">C3-PLL-1</font></td> <td width="25" height="60" background="bar-right.jpg"> </td> </tr> </table> <p> For applications that require frequency multiplication only, Cologne Chip offers moreover <b>C3-PLL-1</b>, a subset of C3-PLL-2. It disposes of the same technical features as C3-PLL-2, but without configuration registers and without predivider and post-scaler. <ul type="square"> <li>Fully digital</li><p> <li> All features like C3-PLL-2 except configuration registers, predivider and post-scaler</li><p> <li> Frequency multiplication range: 5 to 255</li><p> </ul> <p> <p> <table border="0" cellspacing="0" cellpadding="0" cols="3" width="100%"> <tr> <td width="25" height="60" background="bar-left.jpg"> </td> <td height="60" background="bar-middle.jpg"><font face="Arial,Helvetica" color="#FFFFFF" size="+1">Documentation</font></td> <td width="25" height="60" background="bar-right.jpg"> </td> </tr> </table> <p> More detailed technical information upon Cologne Chip's PLL IP cores as well as the datasheets can be downloaded in the following: <p> <table cellpadding="0" cellspacing="0"> <tr><td valign="top" nowrap> <a href="c3-pll-2.pdf" target="top"><b>C3-PLL-2</b></a> <br> Datasheet </td><td> </td> <td valign="top"> (pdf, 780 KB) </td></tr> <tr><td colspan="3"> </td></tr> <tr><td valign="top" nowrap> <a href="c3-pll-1.pdf" target="top"><b>C3-PLL-1</b></a> <br> Datasheet </td><td> </td> <td valign="top"> (pdf, 702 KB) </td></tr> <tr><td colspan="3"> </td></tr> <tr><td valign="top" nowrap> <a href="digicc-pll-techn.pdf" target="top"><b>DIGICC PLL Technology</b></a> <br> Technology Background </td><td> </td> <td valign="top"> (pdf, 594 KB) </td></tr> </table> <p> <p>  <p> <map name="navigation"><area shape="rect" coords="18,72,86,88" href="../../framestart.htm" target="_top"><area shape="rect" coords="14,68,148,93" href="mailto:info@CologneChip.com"><area shape="rect" coords="120,18,148,50" href="#top" target="_self"></map> <table border=0 cellspacing=0 cellpadding=0 cols=2 width="100%"> <tr> <td valign="bottom"><font face="Arial,Helvetica"><font size=-2>Copyright © 2009 Cologne Chip</font></font></td> <td><img src="navigation.jpg" align="right" width=160 height=108 border=0 usemap="#navigation"></td></tr> </table></td></tr><table>