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<td height="60" background="bar-middle.jpg"><font face="Arial,Helvetica" color="#FFFFFF" size="+1">DIGICC - Analog in the Digital Way</font></td>
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<p>
<b>DIGICC</b> is a highly sophisticated new approach for ASIC projects: It meets mixed mode
requirements with pure digital logic.
<p>
Analog functional blocks can now be replaced by a fully digital CMOS design using DIGICC-based ASIC IP cores. Cologne Chip offers these new building blocks for almost all CMOS process technologies - as digital macros are easily scalable over a broad range of chip geometries.
<p>
The innovative IP blocks are not only silicon-proven but can also be evaluated (or even used!) with FPGA technology.
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<img src="digicc-logo-large.png" width="284" height="113" border="0" hspace="10" align="right">
Advantages of <b>DIGICC</b>-based <b>C³IP</b> are
<ul type="square">
<li>easy to integrate into all IC designs</li><p>
<li>independent from process technology and chip geometry</li><p>
<li>persistent high production quality</li><p>
<li>small silicon space</li><p>
</ul>
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Learn more about DIGICC by reading the technology papers on PLLs and CODECs:
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<a href="digicc-pll-techn.pdf" target="top"><b>DIGICC technology for PLLs</b></a>
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(pdf, 594 KB)
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<a href="digicc-codec-techn.pdf" target="top"><b>DIGICC technology for CODECs</b></a>
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(pdf, 605 KB)
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To benefit from the innovative approach of <b>DIGICC</b> technology in your chip design project, find out more about the available IP cores of Cologne Chip:
<p>
<a href="frame-c3-pll.htm" target="_top"><b>C3-PLL-2 and C3-PLL-1</b></a>
<br>
Phase Locked Loop (PLL) frequency synthesizer and multiplier cores
<p>
<a href="frame-c3-codec.htm" target="_top"><b>C3-CODEC-G712-4</b></a>
<br>
Quad Voice CODEC compliant to ITU-T G.712 and G.711
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