DIGICC is a highly sophisticated new approach for ASIC projects: It meets mixed mode requirements with pure digital logic.
Analog functional blocks can now be replaced by a fully digital CMOS design using DIGICC-based ASIC IP cores. Cologne Chip offers these new building blocks for almost all CMOS process technologies - as digital macros are easily scalable over a broad range of chip geometries.
The innovative IP blocks are not only silicon-proven but can also be evaluated (or even used!) with FPGA technology.
Advantages of DIGICC-based C³IP are
Learn more about DIGICC by reading the technology papers on PLLs and CODECs:
To benefit from the innovative approach of DIGICC technology in your chip design project, find out more about the available IP cores of Cologne Chip:
C3-PLL-2 and C3-PLL-1