Cologne Chip - ASIC IP Cores

<a name="top"></a> <table width="100%" > <tr> <td align=left valign="middle" width="15%"></td> <td align=left valign="middle" width="85%"> <p> <table border=0 cellspacing=0 cellpadding=0 cols=3 width="100%"> <tr> <td width="25" height="60" background="bar-left.jpg"> </td> <td height="60" background="bar-middle.jpg"><font face="Arial,Helvetica" color="#FFFFFF" size="+1">Welcome to C3IP</font></td> <td width="25" height="60" background="bar-right.jpg"> </td> </tr> </table> <p> <p> <table border="0" cols="3" width="100%"> <tr> <td valign="top" width="221"> <img src="puzzle.png" width="219" height="450" border="0" align="left"> </td> <td width="20"> </td> <td> Under the name <b>"C³IP"</b> Cologne Chip introduces several ASIC IP cores to the market. The vast experience in ASIC design has led to an in-depth know-how especially in the field of telecommunication interfaces. Successful launches of many ICs and millions of sold microchips underline the company’s expertise in ASIC and FPGA design. <p> <b>Design Approach</b> <p> The first Cologne Chip IP cores are based on the innovative <b>DIGICC</b> technology. Traditionally telecommunication ICs require analog cores making designs inflexible and expensive. New DIGICC-based <b>C³IP</b> does offer fully digital implementations instead of these analog functional blocks. This sounds "impossible" even for the experienced hardware engineer - but it works! <table border="0" align="left" valign="top" cellspacing="0" rows="2" cols="2" cellpadding="0" Width="100%"> <tr><td align="left"> Discover more about the benefits of <b>C³IP</b> on the following pages ... <p> </td></tr> <tr> <td align="left"> <a href="frame-digicc.htm" target="_top"><b>DIGICC Technology</b></a> <br><br><br> The following cores are already available: <p> <a href="frame-c3-pll.htm" target="_top"><b>C3-PLL-2 and C3-PLL-1</b></a> <br> Phase Locked Loop (PLL) frequency synthesizer and multiplier cores <p> <a href="frame-c3-pll.htm" target="_top"><b>C3-PLL-2 and C3-PLL-1</b></a> <br> Phase Locked Loop (PLL) frequency synthesizer and multiplier cores <p> <a href="frame-c3-codec.htm" target="_top"><b>C3-CODEC-G712-4</b></a> <br> Quad Voice CODEC compliant to ITU-T G.712 and G.711 </td> <td align=right> <table border="0" align="right" valign="down" cellspacing="0" rows="3" cols="3" cellpadding="5" Width=350> <tr height="25"> <td width="10" background="../../isdn/controllers/bar-upperleft.gif"> </td> <td background="../../isdn/controllers/bar-uppermiddle.gif"> </td> <td width="15" background="../../isdn/controllers/bar-upperright.gif"> </td> </tr> <tr> <td background="../../isdn/controllers/bar-leftmiddle.gif"> </td> <td align="left"><font face="Arial,Helvetica" size="-1"><b>White Papers on C3IP Technology</b><br> held at IP-SOC 2006, Grenoble<br><br><i><a href="c3-pll-presentation_socip.pdf" target="_top">"Fully Digital Implemented Phase Locked Loop"</a></i><br>by Michael Gude & Gerriet Mueller (pdf, 34 KB)<br><br><i><a href="c3-codec-presentation_socip.pdf" target="_top">"Fully Digital Implemented Delta-Sigma Analog to Digital Converter"</a></i><br>by Michael Gude & Gerriet Mueller (pdf, 229 KB)</font></td> <td background="../../isdn/controllers/bar-rightmiddle.gif"> </td> </tr> <tr height="25"> <td background="../../isdn/controllers/bar-lowerleft.gif"> </td> <td background="../../isdn/controllers/bar-lowermiddle.gif"> </td> <td background="../../isdn/controllers/bar-lowerright.gif"> </td> </tr> </table> </td></tr> <tr><td align="left"> <img src="../../isdn/controllers/space.gif" width="5" height="80"><br> <img src="c3ip.png" width="132" height="112" border="0" align="left" valign="bottom"> </td> <td> <table rows=1 cols=2 border=0 cellpadding=0 cellspacing=0 width=350 align=right valign=down > <tr> <td> <img src="../../isdn/controllers/space.gif" width="5" height="115"><br> <font face="Arial,Helvetica" size="-1"><i> we are IP partner of</i></font><br> <img src="../../isdn/controllers/space.gif" width="5" height="15"><br> <a href="http://www.chipestimate.com/" target="_top"><img src="chipestimate_190.gif" width="132" height="46" border="0" align="left" valign="bottom"></a> </td> <td>   </td> </tr> </Table> </td> </tr> </table> </table>  <p> <map name="navigation"><area shape="rect" coords="18,72,86,88" href="../../framestart.htm" target="_top"><area shape="rect" coords="14,68,148,93" href="mailto:info@CologneChip.com"><area shape="rect" coords="120,18,148,50" href="#top" target="_self"></map> <table border=0 cellspacing=0 cellpadding=0 cols=2 width="100%"> <tr> <td valign="bottom"><font face="Arial,Helvetica"><font size=-2>Copyright © 2007 Cologne Chip</font></font></td> <td><img src="navigation.jpg" align="right" width=160 height=108 border=0 usemap="#navigation"></td></tr> </table> </td></tr></table>