Introduction

Cologne Chip’s IP core C3-CODEC-G712-4 consists of four voice CODECs for telephony applications in compliance with ITU-T recommendation G.712 or G.711.

Usually the ADC and the DAC in a CODEC need analog parts to be integrated into the chip. In contrast C3-CODEC-G712-4 is fully digital. All needed analog functionality is implemented as a few external resistors and capacitors per CODEC. This tiny circuitry is connected to the chip via three digital I/O buffers per CODEC.

The main part of the core area is used for digital filters in the transmit and receive path according to ITU-T recommendation G.712. There are sophisticated digital machines in the frontend of the core to minimize the external component cost. Implementing analog functions into fully digital CMOS circuitries becomes feasible by means of DIGICC, Cologne Chip’s digital approach for IP cores. A patent is pending for this DIGICC technology of Cologne Chip.

Block Diagramm

A functional overview of C3-CODEC-G712-4 is given in the following diagram. It represents the various blocks of this IP core, all being based on the DIGICC design concept of Cologne Chip.

Technical Features

• 4 voice CODECs implemented (ADC / DAC)
• Fully digital
• Interface data format configurable:
  - 16 bit linear or
  - 8 bit a-law / µ-law according to ITU-T recommendation G.711
• Performance of the filters according to ITU-T recommendation G.712
• Implementable in any CMOS process technology
• Implementable also into FPGA with external buffer
• Only 3 digital I/O pins and one power supply pin needed for each CODEC
• Only a few resistors and capacitors per CODEC required as external components
• The signal to total distortion complies to ITU-T recommendation G.712
• Suppression of 50 Hz and 60 Hz in the ADC better than 45 dB
• Separate gains for transmit paths (ADC) and receive paths (DAC) for each CODEC programmable
• Power reduction to nearby zero in stand-by mode possible
• 8 ksample/s or 16 ksample/s internally configurable for 3.1 kHz and 7 kHz audio bandwidth
• Clock frequency: 24.576 MHz
• Area: approx. 60k logic gates + RAM
  RAM: 4 synchronous, single port RAM blocks
  (128x32 bit + 64x32 bit + 64x16 bit + 32x16 bit = 7.68 kbit)
• Core version with only three, two or one CODEC available
  (reducing by one CODEC decreases the core by 6k logic gates and 1.92 kbit RAM)

More detailed technical information upon Cologne Chip's CODEC IP core as well as the datasheet can be downloaded in the following:

Copyright © 2009 Cologne Chip

Last Modified: 25/02/2009