For general purpose Phase Locked Loops (PLLs), ASIC designers have to rely on analog VCOs until today. Now Cologne Chip has come up with a fully digital approach: C3-PLL-2, an IP core for frequency synthesizer applications.

A patent is pending for this innovation of Cologne Chip.

Benefits

C3-PLL-2 relies on the DIGICC design concept of Cologne Chip. This makes it possible to easily implement the core in all process technologies: C3-PLL-2 is a fully digital circuitry using standard cell libraries. Because of its pure digital nature, the PLL does neither need any additional pad or pin nor external or internal loop capacitors. On top of that, normally no external filters for the supply voltage are required.

The lock time of the PLL is very short - it is even super-fast when the PLL is restarted after stand-by mode. Furthermore the silicon space used is smaller than that of competing technologies.

More technical and commercial benefits of C3-PLL compared to conventional PLLs are listed here (pdf, 228 KB).

Technical Features

• Fully digital - designed for use with standard cell libraries for digital logic
• Implementable in any digital CMOS process technology
• Typical oscillator frequency ranges:
  0.50 µm:   60-120 MHz
  0.35 µm: 100-200 MHz
  0.25 µm: 140-280 MHz
  0.18 µm: 160-320 MHz
  0.13 µm: 180-360 MHz
     90 nm: 200-400 MHz
• Frequency multiplication range: 5 to 255
• Predivider and post-scaler with divider range 1..256 each
• Jitter similar to analog PLLs
• No pads, special pins, external loop filter capacity or supply voltage filters needed
• Very fast lock time (worst case 2,000 reference clocks)
• Stand-by mode (oscillator stopped but center frequency adjustments preserved)

> super-fast lock time when returning from stand-by mode (only some clock cycles)

• Stand-by also reduces power to zero (only leakage current)
• Very small area (< 3,000 gates)

For applications that require frequency multiplication only, Cologne Chip offers moreover C3-PLL-1, a subset of C3-PLL-2. It disposes of the same technical features as C3-PLL-2, but without configuration registers and without predivider and post-scaler.

• Fully digital
• All features like C3-PLL-2 except configuration registers, predivider and post-scaler
• Frequency multiplication range: 5 to 255

More detailed technical information upon Cologne Chip's PLL IP cores as well as the datasheets can be downloaded in the following:

Copyright © 2009 Cologne Chip

Last Modified: 25/02/2009