| DIGICC - Analog in the Digital Way |
DIGICC is a highly sophisticated new approach for ASIC projects: It meets mixed mode requirements with pure digital logic.
Analog functional blocks can now be replaced by a fully digital CMOS design using DIGICC-based ASIC IP cores. Cologne Chip offers these new building blocks for almost all CMOS process technologies - as digital macros are easily scalable over a broad range of chip geometries.
The innovative IP blocks are not only silicon-proven but can also be evaluated (or even used!) with FPGA technology.
Advantages of DIGICC-based C³IP are
- easy to integrate into all IC designs
- independent from process technology and chip geometry
- persistent high production quality
- small silicon space
Learn more about DIGICC by reading the technology papers on PLLs and CODECs:
| DIGICC technology for PLLs | (pdf, 594 KB) | |
| DIGICC technology for CODECs | (pdf, 605 KB) | |
To benefit from the innovative approach of DIGICC technology in your chip design project, find out more about the available IP cores of Cologne Chip:
C3-PLL-2 and C3-PLL-1
Phase Locked Loop (PLL) frequency synthesizer and multiplier cores
C3-CODEC-G712-4
Quad Voice CODEC compliant to ITU-T G.712 and G.711
| Copyright © 2005 Cologne Chip | Last Modified: 08/06/2005 |  |