Cologne Chip

Welcome to C3IP

Under the name "C³IP" Cologne Chip introduces several ASIC IP cores to the market. The vast experience in ASIC design has led to an in-depth know-how especially in the field of telecommunication interfaces. Successful launches of many ICs and millions of sold microchips underline the company’s expertise in ASIC and FPGA design.

Design Approach

The first Cologne Chip IP cores are based on the innovative DIGICC technology. Traditionally telecommunication ICs require analog cores making designs inflexible and expensive. New DIGICC-based C³IP does offer fully digital implementations instead of these analog functional blocks. This sounds "impossible" even for the experienced hardware engineer - but it works!

Discover more about the benefits of C³IP on the following pages ...

DIGICC Technology

The following cores are already available:

C3-PLL-2 and C3-PLL-1

Phase Locked Loop (PLL) frequency synthesizer and multiplier cores

C3-CODEC-G712-4

Quad Voice CODEC compliant to ITU-T G.712 and G.711


	White Papers on C3IP Technology presented at IP-SOC 2006, Grenoble "Fully Digital Implemented Phase Locked Loop" by Michael Gude & Gerriet Mueller (pdf, 34 KB) "Fully Digital Implemented Delta-Sigma Analog to Digital Converter" by Michael Gude & Gerriet Mueller (pdf, 229 KB)

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Last Modified: 20/06/2007