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Functions
The HFC is a HDLC B-channel controller. Two B-channels are served full
duplex by 4 deep FIFOs. Also implemented is a PC ISA bus interface.
Features
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FIFO-Depth:
7.5 KByte per channel and direction with 32 KByte external RAM
1.5 KByte per channel and direction with 8 KByte external RAM
maximum 31 HDLC frames per FIFO
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2 Read/Write HDLC controllers for the B-channels (zero insertion and CRC);
serves B1 und B2 independently; B1 and B2 transparent mode independently
selectable.
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8-Bit ISA bus interface with line transceiver for data bus or microprocessor
interface; one of 6 interrupt channels selectable by software, additionally
one timer (25/50ms).
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only 2 I/O addresses used on PC ISA bus; I/O addresses programmable (no
memory mapping, no DMA)
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CMOS technology 3V-5V, case QFP 80
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