Cologne Chip - XHFC-1SU ISDN Controller IC

<a NAME="top"></a> <table WIDTH="100%"> <tr> <td ALIGN=LEFT VALIGN=middle WIDTH="15%"> </td> <td ALIGN=LEFT VALIGN=middle WIDTH="85%"> <P> <table BORDER=0 CELLSPACING=0 CELLPADDING=0 COLS=3 WIDTH="100%"> <tr> <td BACKGROUND="bar-left.jpg" width="25" HEIGHT=60> </TD> <td BACKGROUND="bar-middle.jpg" HEIGHT=60><FONT FACE="Arial,Helvetica"><FONT SIZE="+1"><FONT COLOR="#FFFFFF">XHFC-1SU</FONT></FONT></FONT></TD> <td BACKGROUND="bar-right.jpg" width="25" HEIGHT=60> </TD> </table> <P>  <H3><img src="new-2.gif" width="105" height="84" align="right" hspace="10" vspace="10"> Functions</H3> The XHFC-1SU is an ISDN transceiver chip for one ISDN S/T or U<sub>pN</sub>/U<sub>p0</sub> Basic Rate Interface with integrated HDLC controllers for all kinds of BRI equipment. The integrated microprocessor bus interface of the XHFC-1SU can be configured to 8 bit parallel microprocessor interface or serial processor interface (SPI). A PCM128 / PCM64 / PCM30 interface for CODEC or inter-chip connection is also integrated. The deep FIFOs of the XHFC-1SU are realized with an internal SRAM. <p>  <H3> Block Diagram</H3> <img SRC="xhfc-1su.gif" ALT="XHFC-1SU Block Diagram" height="417" width="649" border="0"> <p>  <H3>Features</H3> <UL TYPE=SQUARE> <font color="#ffffff"> <li> <b><font color="#000000">Line interfaces</font></b></li></font> <img src="universal-isdn-port.png" width="110" height="52" border="0" HSPACE=15 VSPACE=10 align="right"> <p> <li> 1 ISDN interface selectable as S/T or U<sub>pN</sub>/U<sub>p0</sub> interface (Universal ISDN Port)</li> <li> S/T ISDN interface in TE and NT mode conform to ITU-T I.430 and TBR 3</li> <li> U<sub>p</sub> signal range exceeding U<sub>pN</sub>/U<sub>p0</sub> specification</li> <li> simple external line interface circuitry</li><p> <font color="#ffffff"> <li> <b><font color="#000000">HDLC-controller and FIFO controller</font></b></li></font><p> <li> universal HDLC controller for both B-channels, D- and E-channel, can also be used for PCM time slots</li> <li> transparent mode and data rate independently selectable for all FIFOs</li> <li> up to 16 FIFOs for transmit and receive data each, FIFO size configurable from 64 up to 256 bytes per FIFO, maximum 7 HDLC frames per FIFO</li> <li> B- and D-channels can be combined for higher data rate to 128 kBit/s (2B) or 144 kBit/s (2B+D)</li> <li> Bit Error Rate Test (BERT) with transmitter and receiver</li> <li> programmable data flow to connect FIFOs, ST / U<sub>p</sub> interface and PCM time slots with each other</li><p> <font color="#ffffff"> <li> <b><font color="#000000">PCM interface</font></b></li></font><p> <li> PCM128 / PCM64 / PCM30 interface configurable to MST (MVIP)<sup>TM</sup> or Siemens IOM-2<sup>TM</sup> and Motorola GCI<sup>TM</sup> (monitor and C/I-channel support) for interchip connection or external CODECs</li> <li> programmable PCM time slot assigner for 16 channels in transmit and receive direction each (switch matrix for PCM)</li> <li> H.100 data rate supported on PCM bus</li> <li> flexible PCM synchronization options implemented, synchronization input and output signals available</li><p> <font color="#ffffff"> <li> <b><font color="#000000">Microprocessor bus interface</font></b></li></font><p> <li> improved 8 bit parallel microprocessor interface compatible to Motorola bus and Siemens / Intel bus, multiplexed and non-multiplexed modes supported</li> <li> high performance serial processor interface (SPI), up to 16 XHFC devices addressable with one /SPISEL signal</li> <li> auto-configure mode for repeater applications without microcontroller (only external EEPROM needed)</li><p> <font color="#ffffff"> <li> <b><font color="#000000">Miscelleanous features</font></b></li></font><p> <li> flexible interrupt controller, timer and watchdog with interrupt capability</li> <li> programmable PLL with big range of clock frequencies for general purpose usage (can also be used to generate the internal system clock)</li> <li> 6 dedicated GPIO pins available, 6 additional pins can be used for GPIO when the line interface is not used, further 8 GPIOs can be enabled separately as second pin function</li> <li> 2 general purpose pulse width modulators (PWM) with dedicated output pins</li><p> <font color="#ffffff"> <li> <b><font color="#000000">Technology features</font></b></li></font> <img src="rohs-logo-new.gif" width="106" height="68" align="right" hspace="10" vspace="10"> <p> <li> single 3.3V power supply, CMOS technology 3.3V, 5V tolerant on nearly all inputs</li> <li> LQFP 64 package, 0.5mm pin pitch</li> <li> RoHS compliant</li> </UL> <p>  <H3>Applications</H3> <UL TYPE=SQUARE> <li> VoIP gateways / VoIP routers</li><p> <li> Integrated Access Devices (IAD)</li><p> <li> ISDN SOHO PABX</li><p> <li> ISDN phones / system phones</li><p> <li> POTS TAs</li><p> <li> POS terminals</li><p> <li> ISDN least cost routers</li><p> <li> ISDN LAN routers</li><p> <li> ISDN test equipment</li> </UL> <p>  <p>  <table border="0" width="100%" cellpadding="0" cellspacing="0"> <tr> <td align="left" valign="top"> <H3>Linux Driver</H3> A generic <a href="frame-linuxdriver.htm" target="_top">Linux driver</a> for XHFC-1SU is available upon request. </td><td align="right" valign="top"> <img src="penguin.gif" width="60" height="70"> </td> </tr> </table> <p>  <p>  <table border="0" cellpadding="0" cellspacing="0"> <tr> <td> <img src="evalboard-xhfc-1su-small.jpg" width="171" height="125" border="0" alt="Evaluation board of XHFC-1SU" align="left">   </td> <td align="left" valign="bottom"> <h3>Evaluation Board</h3> <a href="mailto:info@CologneChip.com">Contact us</a> for an evaluation board of XHFC-1SU. </td> </tr></table> <p>  <H3>Datasheet</H3> <A HREF="main-datasheets.htm#xhfc-1su">Get Datasheet</A> <P>  <MAP NAME="navigation"><AREA SHAPE="rect" coords="18,72,86,88" href="../../framestart.htm" target="_top"><AREA SHAPE="rect" coords="14,68,148,93" HREF="mailto:info@CologneChip.com"><AREA SHAPE="rect" coords="120,18,148,50" href="#top" target="_self"></MAP> <TABLE BORDER=0 CELLSPACING=0 CELLPADDING=0 COLS=3 WIDTH="100%"> <TR> <TD VALIGN="bottom"><FONT FACE="Arial,Helvetica"><FONT SIZE=-2>Copyright © 2007 Cologne Chip<BR>The ISDN Chip Company!</FONT></FONT></TD> <td VALIGN=BOTTOM><font face="Arial,Helvetica"><font size=-2>Last Modified: 02/02/2007</font></font></td> <TD><IMG SRC="navigation.jpg" width="160" height="108" ALIGN="right" BORDER=0 USEMAP="#navigation"></TD></TR> </TABLE> </td></tr> </table>  <BR> <HR> <P ALIGN=CENTER> [<A HREF="frame-news.htm">News</A>] [<A HREF="frame-overview.htm">Overview</A>] [<A HREF="frame-chips.htm">ISDN Controllers</A>] [<A HREF="frame-datasheets.htm">Datasheets</A>] <BR> [<A HREF="frame-applications.htm">Applications</A>] [<A HREF="frame-software.htm">Driver Software</A>] [<A HREF="frame-transformers.htm">Transformers</A>] [<A HREF="frame-approval.htm">ISDN Type Approval</A>] <BR> [<A HREF="frame-distributors.htm">Distributors</A>] [<A HREF="frame-contact.htm">Contact</A>] [<A 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