The XHFC-2SU is an ISDN transceiver chip for two ISDN S/T or UpN/Up0 Basic Rate Interfaces
with integrated HDLC controllers for all kinds of BRI equipment.
The integrated microprocessor bus interface of the XHFC-2SU can be configured to
8 bit parallel microprocessor interface or serial processor interface (SPI).
A PCM128 / PCM64 / PCM30 interface for CODEC or inter-chip connection is also integrated.
The deep FIFOs of the XHFC-2SU are realized with an internal SRAM.
- 2 ISDN interfaces, both selectable as S/T or UpN/Up0 interfaces (Universal ISDN Ports)
- S/T ISDN interfaces in TE and NT mode conform to ITU-T I.430 and TBR 3
- Up signal range exceeding UpN/Up0 specification
- simple external line interface circuitry
HDLC-controller and FIFO controller
- universal HDLC controller for all B-, D- and E-channels, can also be used for PCM time slots
- transparent mode and data rate independently selectable for all FIFOs
- up to 16 FIFOs for transmit and receive data each, FIFO size configurable from 64 up to 256 bytes per FIFO, maximum 7 HDLC frames per FIFO
- B- and D-channels can be combined for higher data rate to 128 kBit/s (2B) or 144 kBit/s (2B+D) per line interface
- Bit Error Rate Test (BERT) with transmitter and receiver
- programmable data flow to connect FIFOs, ST / Up interfaces and PCM time slots with each other
- PCM128 / PCM64 / PCM30 interface configurable to MST (MVIP)TM or Siemens IOM-2TM and Motorola GCITM (monitor and C/I-channel support) for interchip connection or external CODECs
- programmable PCM time slot assigner for 16 channels in transmit and receive direction each (switch matrix for PCM)
- H.100 data rate supported on PCM bus
- flexible PCM synchronization options implemented, synchronization input and output signals available
Microprocessor bus interface
- improved 8 bit parallel microprocessor interface compatible to Motorola bus and Siemens / Intel bus, multiplexed and non-multiplexed modes supported
- high performance serial processor interface (SPI), up to 16 XHFC devices addressable with one /SPISEL signal
- auto-configure mode for repeater applications without microcontroller (only external EEPROM needed)
- flexible interrupt controller, timer and watchdog with interrupt capability
- programmable PLL with big range of clock frequencies for general purpose usage (can also be used to generate the internal system clock)
- 6 GPIO pins can be used instead of every unused line interface, further 8 GPIOs can be enabled separately as second pin function
- 2 general purpose pulse width modulators (PWM) with dedicated output pins
- single 3.3V power supply, CMOS technology 3.3V, 5V tolerant on nearly all inputs
- LQFP 64 package, 0.5mm pin pitch
- RoHS compliant
- VoIP gateways / VoIP routers
- Integrated Access Devices (IAD)
- ISDN PABX
- IP Centrex / Hosted PBX
- ISDN least cost routers
- ISDN LAN routers
- ISDN test equipment
- Call recording
- S/T-to-Up converters (private NTs)
- Up repeaters
Generic Linux drivers for XHFC-2SU are available upon request.
Contact us for an evaluation board of XHFC-2SU.
Copyright © 2011 Cologne Chip
The ISDN Chip Company!
Last Modified: 03/05/2011
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