Cologne Chip

HFC-8S

Functions

The HFC-8S is a HDLC B- and D-channel controller with 8 integrated S/T interfaces. It can be used for ISDN basic rate lines. All channels are served fully duplex by deep FIFOs. Also implemented is a PCM128 / PCM64 / PCM30 highway interface (which is able to connect to many telecom serial busses) and an universal external bus interface.

Block Diagram

Features

single chip ISDN-S/T-controller with B- and D-channel HDLC support

8 integrated S/T interfaces

full I.430 ITU S/T ISDN support in TE and NT mode

32 independent read and write HDLC-channels
for e.g. 16 ISDN B-channels, 8 ISDN D-channels and 8 timeslots on the PCM interface

transparent mode for each B-channel independently selectable

up to 64 FIFOs; FIFO-size configurable

each FIFO can be assigned to an arbitrary channel of any S/T or PCM interface

max. 31 HDLC frames (with external 128k or 512k RAM) or 15 HDLC frames (with 32k built-in RAM) per FIFO

1 - 8 bit processing for subchannels selectable

56 KBit/s restricted mode for U.S. ISDN lines selectable

B-channels for higher data rate combinable

PCM128 / PCM64 / PCM30 interface configurable to interface MITEL ST^TM bus (MVIP^TM) or Siemens IOM2^TM and Motorola GCI^TM (bearer slots supported only) for inter-chip connection (e.g. external CODECs)