HFC-S active  


The HFC-S active is not recommended for new projects. Please use XHFC-1SU instead in combination with a suitable CPU.
 

Functions

The HFC-S active is an ISDN telecommunication microprocessor system on a single chip (SoC). It is based on a powerful 32-Bit ARM7TDMI RISC processor with 16- and 32-bit instruction set. This industrial standard processor includes on-chip debugging facilities (embedded ICE).
The HFC-S active microprocessor system includes a 16 kByte high speed memory, a S/T interface with layer 1 and layer 2 functions for the D, B1 and B2 channel, a full speed USB-interface and a standard RS232 interface. The CPU can boot from external Flash or from the RS232 interface.
The integrated CODECs allow the connection to telephone hand-sets or POTS ports in PABX applications. The CODECs have a programmable power-down mode. A processor controlled power management is supported. The programmable PLL allows to vary the system clock speed in the range from 12.288 MHz to 49.152 MHz.

 

Block Diagram

HFC-S active Block Diagram

 

Features

  • The HFC-S active contains a powerful 32-bit ARM7TM RISC controller with a 32-bit address-space operating at up to 49.152 MHz in worst case commercial conditions.

  • Internal 16 KBytes SRAM (zero wait states)

  • Supports 8/16-bit SRAM/Flash/SDRAM external memory

  • Advanced SDRAM controller with minimum wait states (full column burst mode)

  • 5 independent external address spaces with software programmable wait state generation

  • Integrated ISDN S/T-controller with B- and D-channel HDLC support

  • Full I.430 ITU S/T ISDN support in TE and NT mode

  • 6 independent read and write HDLC-controllers for B1, B2 and D-channel

  • B1, B2 and D-channel transparent mode independently selectable

  • Integrated FIFOs: 64 bytes per channel and direction

  • 2 integrated audio CODECs for connection of analog devices (e.g. phone, fax, answering machine in PABX applications or handset in telephone applications)

  • 3 independently programmable PCM highways with programmable switching units between the 3x32 PCM highway-channels (timeslots), the B1 and B2- channels of the S/T-interface and the 2 CODEC data registers

  • Integrated high speed RS232 interface (UART) with programmable data rate from 1.2 kbaud to 230.4 kbaud (theoretical maximum data rate: 1/8 of the system frequency)

  • ROM-code for UART boot option integrated

  • Full speed 12 Mbps Universal Serial Bus (USB) interface integrated with 8 data endpoints with 64 byte FIFO per direction and 1 control endpoint with 64 byte FIFO per direction (USB specification 1.1 compliant)

    • Supports isochronous and non-isochronous data
    • Bidirectional half-duplex link
    • On-chip USB transceiver
    • Serial bus interface engine with packet decoding/generation, CRC generation and checking, NRZI encoding/ decoding and bit-stuffing

  • 2 programmable 16 bit timers with 8 bit prescaler with interrupt capability

  • 16 bit programmable PWM-counter with interrupt capability

  • Watchdog timer with interrupt capability and reset generation capability

  • Up to 31 GPIO pins, 16 of these with interrupt capability

  • Flexible and efficient interrupt processing for all system modules

  • CMOS technology

  • PQFP 160 case, RoHS compliant

 

Applications

  • ISDN telephones with data port

  • ISDN PABX and ISDN POTS terminal adapters

  • ISDN USB terminal adapters

  • ISDN RS232 terminal adapters

  • various other ISDN applications by using external peripherals (e.g. ISDN LAN router)

 

Evaluation kit for HFC-S active   

Evaluation Kit

Information about the evaluation kit for HFC-S active

 

Datasheet

Get Datasheet

 

 

Copyright © 2006 Cologne Chip
The ISDN Chip Company!		 Last Modified: 22/06/2006