HFC-SP  


The HFC-SP is not recommended for new projects.
This chip is not available in a lead-free version.
 

Functions

The HFC-SP is a HDLC B- and D-channel controller with integrated S/T interface. It can be used for ISDN basic rate lines. All channels (2B+D) are served fully duplex by six deep FIFOs. The HFC-SP has an integrated ISA Plug and Play and a PCMCIA interface. Also implemented is a PCM30 highway interface (which is able to connect to many telecom serial busses) and a microprocessor interface.

 

Block Diagram

HFC-SP Block Diagram

 

Features

  • single chip ISDN-S-controller with B- and D-channel HDLC support

  • integrated S/T interface

  • independent read and write HDLC-channels for 2 ISDN B-channels and one ISDN D-channel

  • B1 and B2 transparent mode independently selectable

  • FIFO-Depth:
    • B-channel: 4x 7.5 KByte, maximum 31 HDLC frames per FIFO 
    D-channel: 2x 512 Byte, maximum 15 HDLC frames per FIFO 

  • 56 KBit/s restricted mode for U.S. ISDN lines selectable by software

  • full I.430 ITU S/T ISDN support in TE and NT mode for 3.3V and 5V power supply

  • B1+B2 HDLC mode

  • PCM30 interface configurable to interface MITEL STTM bus (MVIPTM), Siemens IOM2TM or GCITM for interface to U-chip or external CODECs

  • direct 8 bit ISA-PC bus interface with buffers for ISA-databus 

  • integrated ISA Plug and Play (Windows 95 Spec.)

  • only 2 I/O addresses used on ISA-PC bus

  • one of 7 interrupt channels on ISA-PC bus selectable by software

  • integrated PCMCIA interface

  • microprocessor interface compatible to Motorola bus and Siemens/Intel bus

  • simple access to PCM30 interface for tone synthetisation

  • timer with interrupt and watchdog capability in processor mode

  • CMOS technology 3-5V

  • case QFP 100

 

Applications

 

Linux Driver

A generic Linux driver is available for HFC-SP.

 

Datasheet

Get Datasheet

 

 

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