Cologne Chip

XHFC-1SU

Functions

The XHFC-1SU is an ISDN transceiver chip for one ISDN S/T or U_pN/U_p0 Basic Rate Interface with integrated HDLC controllers for all kinds of BRI equipment. The integrated microprocessor bus interface of the XHFC-1SU can be configured to 8 bit parallel microprocessor interface or serial processor interface (SPI). A PCM128 / PCM64 / PCM30 interface for CODEC or inter-chip connection is also integrated. The deep FIFOs of the XHFC-1SU are realized with an internal SRAM.

Block Diagram

Features

Line interfaces

1 ISDN interface selectable as S/T or U_pN/U_p0 interface (Universal ISDN Port)
S/T ISDN interface in TE and NT mode conform to ITU-T I.430 and TBR 3
U_p signal range exceeding U_pN/U_p0 specification
simple external line interface circuitry

HDLC-controller and FIFO controller

universal HDLC controller for both B-channels, D- and E-channel, can also be used for PCM time slots
transparent mode and data rate independently selectable for all FIFOs
up to 16 FIFOs for transmit and receive data each, FIFO size configurable from 64 up to 256 bytes per FIFO, maximum 7 HDLC frames per FIFO
B- and D-channels can be combined for higher data rate to 128 kBit/s (2B) or 144 kBit/s (2B+D)
Bit Error Rate Test (BERT) with transmitter and receiver
programmable data flow to connect FIFOs, ST / U_p interface and PCM time slots with each other

PCM interface

PCM128 / PCM64 / PCM30 interface configurable to MST (MVIP)^TM or Siemens IOM-2^TM and Motorola GCI^TM (monitor and C/I-channel support) for interchip connection or external CODECs
programmable PCM time slot assigner for 16 channels in transmit and receive direction each (switch matrix for PCM)
H.100 data rate supported on PCM bus
flexible PCM synchronization options implemented, synchronization input and output signals available

Microprocessor bus interface

improved 8 bit parallel microprocessor interface compatible to Motorola bus and Siemens / Intel bus, multiplexed and non-multiplexed modes supported
high performance serial processor interface (SPI), up to 16 XHFC devices addressable with one /SPISEL signal
auto-configure mode for repeater applications without microcontroller (only external EEPROM needed)

Miscelleanous features

flexible interrupt controller, timer and watchdog with interrupt capability
programmable PLL with big range of clock frequencies for general purpose usage (can also be used to generate the internal system clock)
6 dedicated GPIO pins available, 6 additional pins can be used for GPIO when the line interface is not used, further 8 GPIOs can be enabled separately as second pin function
2 general purpose pulse width modulators (PWM) with dedicated output pins