GateMateTM FPGA Series: Feature Summary by Device
The Cologne Chip GateMateTM family addresses a complete range of system requirements. The following table compares all available devices:
Device | Rel. size | Programmable Elements (CPE) 1) 2) |
Block RAM 3) | PLLs | SERDES | I/Os | Package | |||||
CPEs | 8-Inp-LUT trees | FF/Latches | 20Kb | 40Kb | single-ended | differential (LVDS) |
balls | size (mm) | ||||
CCGM1A1 | 1 | 20,480 | 20,480 | 40,960 | 64 | 32 | 4 | 1 | 162 | 81 | 324BGA | 15x15 |
CCGM1A2 | 2 | 40,960 | 40,960 | 81,920 | 128 | 64 | 8 | 2 | 162 | 81 | 324BGA | 15x15 |
CCGM1A4 | 4 | 81,920 | 81,920 | 163,840 | 256 | 128 | 16 | 4 | 154 | 77 | 324BGA | 15x15 |
CCGM1A9 | 9 | 184,320 | 184,320 | 368,640 | 576 | 288 | 36 | 9 | tba | tba | tba | tba |
CCGM1A16 | 16 | 327,680 | 327,680 | 655,360 | 1,024 | 512 | 64 | 16 | tba | tba | tba | tba |
CCGM1A25 | 25 | 512,000 | 512,000 | 1,024,000 | 1,600 | 800 | 100 | 25 | tba | tba | tba | tba |
1) CPEs have 2x4 or 8 inputs connected to a LUT tree 2) Each CPE can be used as 2x2 bit multiplier tile 3) Block RAM can have a max. data width of 20 either 40 Bits