XHFC-1SU
Recommended for new projects
- In mass production
- Available from stock in volumes
Benefits
- Low power consumption
- Easy inter-chip connection to telecom ICs
- Fully digital chip architecture
- Excellent lead times
- Competitive price
- Comprehensive software support
Summary
The XHFC-1SU is a single-chip ISDN transceiver for one ISDN S/T or UpN/Up0 Basic Rate Interface with integrated HDLC controller for all kinds of BRI equipment.
The integrated microprocessor bus interface of the XHFC-1SU can be configured to 8 bit parallel microprocessor interface or serial processor interface (SPI). A PCM128 / PCM64 / PCM30 interface for CODEC or inter-chip connection is also integrated. The deep FIFOs of the XHFC-1SU are realized with an internal SRAM.
Parametrics
| Technology Element | Details |
| S/T interfaces | 1 |
| UpN/Up0 interfaces | 1 |
| Bus interfaces | SPI, 8 bit parallel |
| CODEC or inter-chip connection | PCM128 / PCM64 / PCM30 |
| Package | LQFP 64 |
Evaluation Board
The XHFC-1SU Evaluation Board offers an immediate start of the development of your product. Different line interface subassemblies are available and must be piggypacked onto the XHFC-1SU Evaluation Board.
The XHFC-1SU Evaluation Board is made of the following functional parts:
- the XHFC-1SU microchip
- a socket to mount a line interface subassembly
- a socket for a power feeding module (optional)
- a connector to the host processor system
- a PCM interface connector
Software
Driver software plays an important role in all ISDN projects. This consideration leads to one of the basic principles of Cologne Chip: individual support for each project.
By having broad knowledge about ISDN applications, the support team of Cologne Chip will assist in finding the best approach regarding system architecture and concerning software aspects.
Linux drivers are available for all chips as open source software. Under the terms of GPL (GNU Public Licence) the source code of the Linux drivers may be used free of royalities.
Wheter a project is done as an in-house development or in cooperation with a design house as 3rd-party, Cologne Chip is committed to in-depth technical support for fast time-to-market.
Go to the official repository.
Transformer Selection Guide
Customers of Cologne Chip can choose from a variety of transformers. The relevant requirements for selecting the right transformer for each ISDN Interface are as follows:
Basic Rate (S/T)
compatible to XHFC and HFC series
- Turns ratio of 1:2 (line side : chip side)
- Center tap on chip side (required for Cologne Chip receiver circuitry)
2-wire Basic Rate (Up0/UpN)
compatible to XHFC series
- Turns ratio of 1:1 (line side : chip side)
- Two separated windings (resp. a centre tap) on chip side (required for Cologne Chip receiver circuitry)
Several companies provide transformers and transformer modules that can be used with our ISDN Basic Rate and Primary Rate Interface controllers. Most popular are SMD modules with chokes for EMI reasons.
Here you can find all relevant documentation of XHFC-1SU. Files are gouped by topic, so you will have quick access to the requested information. Please feel free to contact us for any questions.
Note: Data can change without notice. Parts of the information presented may be protected by patent or other rights.
Datasheet
Environmental Documentation
Type Approval
Evaluation
XHFC-1SU Evaluation Board- ST/Up Port Line Interface Subassembly with Coding Plug
- UpN/Up0 Port Line Interface Subassembly
Application Note
Packaging Regulations of XHFC-1SU and XHFC-2SU
XHFC-1SU and XHFC-2SU come on trays in vacuum sealed packages according to industry standards. Please have a look at the packaging regulations:
- LQFP 64 package
- Pin pitch: 0.5 mm
- JEDEC tray
- MSL 3
- Ordering Code: XHFC-1SU / XHFC-2SU
- Country of Origin: Taiwan (TW)
- HS Code: 854231
- RoHS/REACH compliant
Packaging Regulations
Environmental Documentation
Profiles for soldering reflow of XHFC-1SU and XHFC-2SU
The recommended profiles for soldering reflow of XHFC-1SU / XHFC-2SU for Pb-free assembly as well as Sn-Pb eutectic mainly correspond to the commonly applied JEDEC Standard JSTD-020C. To ensure best surface mounting quality, it is recommended to use the provisions of Pb-free assembly. The soldering profile graph (1.) and table (2.) underneath illustrate the respective soldering reflow.
Surface mount products may have a crack when thermal stress is applied during surface mount assembly if they have absorbed atmospheric moisture. It is recommended that these products are handled under specific conditions.
These conditions are described in the following handling recommendations in table (3.).
1. Soldering Profile Graph
Profile for Soldering Reflow
2. Soldering Profile Table
Details Soldering Reflow Profile
| Profile Feature |
Pb-free assembly | Sn-Pb eutectic assembly |
| Average ramp-up rate (TL to TP) | 3°C/second max. | 3°C/second max. |
| Preheat - Temperature Min (TSMIN) - Temperature Max (TSMAX) - Time (min to max) (tS) |
150°Cc 200°Cc 60-180 secondsc |
100°Cc 150°Cc 60-120 secondsc |
| TSMAX to TL – Ramp-up Rate |
3°C/second max | |
| Time maintained above: - Temperature (TL) - Time (tL) |
217°Cc 60-150 secondsc |
183°Cc 60-150 seconds |
| Peak Temperature (TP) | 260 +0/-5°C | 240 +0/-5°C |
| Time within 5°C of actual Peak Temperature (tP) | 20-40 seconds | 10-30 seconds |
| Ramp-down Rate | 6°C/second max. | 6°C/second max. |
| Time 25°C to Peak Temperature | 8 minutes max. | 6 minutes max. |
3. Handling recommendations
Handling recommendations
| Package Type |
Storage Condition
after unpacking
as maximum
|
Rebake Condition
as minimum
|
| LQFP 64 (Pb-free) |
Within 168 hours
(30 °C/60% RH)
MSL 3
|
125 °C
24 hours
|
Documentation