GateMate FPGA


Empowering Innovation, Our FPGA Solution: Ideal for Seamless Integration in Projects of Every Scale, from small to High-Volume Applications.

The GateMateTM FPGA family of Cologne Chip AG addresses all application requirements of small to medium size FPGAs. Logic capacity, power consumption, package size and PCB compatibility are best in class. GateMateTM FPGAs combine these features with lowest cost in industry making the devices well suited from University projects to high volume applications. Because of the outstanding circuit size/cost ratio, new applications now can use the benefits of FPGAs.
All this is based on a novel FPGA architecture combining CPE programmable elements with a smart routing engine. The CPE architecture allows an efficient building of arbitrarily-sized multipliers. Memory aware applications can use block RAMs with bit widths of 1 to 80 bits.

General Purpose IOs (GPIOs) can use different voltage levels from 1.2 to 2.5 Volt. All GPIOs can be configured as single-ended or LVDS differential pairs. Furthermore a high speed SerDes interface is available.
FPGA designs are synthesized using the Yosys framework. The free Cologne Chip P&R-software generates the FPGA bitstream.
A Static Timing Analysis (STA) is also performed and gives evidence about critical paths and the overall performance of a design. The design can be simulated using Verilog netlist and SDF timing extraction.
The devices are manufactured using GlobalfoundriesTM 28 nm SLP (Super Low Power) process. Due to manufacturing in Europe, there is no danger of trade restrictions or high taxation.

GateMateTM FPGA Overview

The GateMate A1 FPGA is the smallest-dimensioned component of the GateMateTM Series. With its 20,480 logic elements, it is ideally suited for lowest-power applications.

CCGM1A1 Parameter
Logic Cells 20,480 CPE correspond to
* 20,480 8-Input-LUT trees or
* 40,960 4-Input-LUT trees with

* 40,960 FF/Latches
Block RAM Total 1,280 Kb
20Kb blocks: 64
40Kb blocks: 32
PLLs 4
SerDes 5 Gb/s 1
I/Os single-ended: 162
differential: 81
1.2V to 2.5V
double data rate (DDR) support
Performance Modes Low Power, Economy, Speed
(0.9V - 1.1V)
Package 324 balls 0.8mm fine pitch ball grid array (FBGA), 15x15 mm