GateMateTM FPGA
Suitable from university projects up to high volume applications
The GateMateTM FPGA family of Cologne Chip AG addresses all application requirements of small to medium size FPGAs. Logic capacity, power consumption, package size and PCB compatibility are best in class. GateMateTM FPGAs combine these features with lowest cost in industry making the devices well suited from University projects to high volume applications. Because of the outstanding circuit size/cost ratio, new applications now can use the benefits of FPGAs.
All this is based on a novel FPGA architecture combining CPE programmable elements with a smart routing engine. The CPE architecture allows an efficient building of arbitrarily-sized multipliers. Memory aware applications can use block RAMs with bit widths of 1 to 80 bits.
General Purpose IOs (GPIOs) can use different voltage levels from 1.2 to 2.5 Volt. All GPIOs can be configured as single-ended or LVDS differential pairs. Furthermore a high speed SerDes interface is available.
FPGA designs are synthesized using the Yosys framework. The free Cologne Chip P&R-software generates the FPGA bitstream.
A Static Timing Analysis (STA) is also performed and gives evidence about critical paths and the overall performance of a design. The design can be simulated using Verilog netlist and SDF timing extraction.
The devices are manufactured using GlobalfoundriesTM 28 nm SLP (Super Low Power) process. Due to manufacturing in Europe, there is no danger of trade restrictions or high taxation.
GateMateTM FPGA Overview
The CCGM1A1 FPGA is the smallest-dimensioned component of the GateMateTM Series. With its 20,480 logic elements, it is ideally suited for lowest-power applications.
CCGM1A1 Parameter |
Detail |
Logic Cells | 20,480 CPE correspond to * 20,480 8-Input-LUT trees or * 40,960 4-Input-LUT trees with * 40,960 FF/Latches |
Block RAM | Total 1,280 Kb 20Kb blocks: 64 40Kb blocks: 32 |
PLLs | 4 |
SerDes 2.5 Gb/s | 1 |
I/Os | single-ended: 162 differential: 81 1.2V to 2.5V double data rate (DDR) support |
Performance Modes | Low Power, Economy, Speed (0.9V - 1.1V) |
Package | 324 balls 0.8mm fine pitch ball grid array (FBGA), 15x15 mm |
GateMateTM FPGA Features
Novel CPE Architecture
- 20,480 programmable elements (CPE) for combinatorial and sequential logic
- 40,960 Latches / Flip-Flops within programmable elements
- CPE consists of LUT-tree with 8 inputs
- Each CPE configurable as 2-bit full-adder or 2x2-bit multiplier
Low Power Consumption
- GlobalfoundriesTM 28 nm SLP (Super Low Power) process
- 3 operation modes: low power, economy, speed
- No excessive start-up currents
- Only two supply voltages needed, can be applied in any order
Features
- 4 programmable PLLs
- Fast configuration with quad SPI interface up to 100 MHz
- Multi-Chip configuration
- 1,280 Kbit dual ported block RAM with variable data widths in 32 x 40 Kbit RAM cells
- Multipliers with arbitrary size implementable in CPE array
- Multiple clocking schemas
- All 162 GPIOs configurable as single-ended or LVDS differential pairs
- Double data rate (DDR) support in all GPIO cells
- 2.5 Gb/s SerDes
Package
- 324-ball BGA package (15x15 mm)
- Only 2 signal layers required on PCB
Here you can find all relevant documentation for GateMateTM FPGA. Files are gouped by topic, so you will have quick access to the requested information. Please feel free to contact us for any questions.
Note: Data can change without notice. Parts of the information presented may be protected by patent or other rights.
GateMateTM Evaluation Board
Start directly with your application development! The GateMateTM Evaluation Board is a feature-rich, ready-to-use development platform for the CCGM1A1.
It serves as a reference design and for a direct entry into application development. User applications can be tailored to each of the six available I/O banks. Attaching additional hardware is a breeze thanks to the Pmod connectors: They allow access to a variety of peripheral boards, including motor controllers, sensors, displays and more.
Interfaces
- Six sophisticated I/O banks
- Two standard 12-pin Pmod connectors
- One high-speed 2.5 Gb/s SerDes connector
- Access to all four clock inputs
- Configuration via flash or on-board USB to SPI/JTAG bridge
Memory
- 64 Mbit Quad-I/O SPI flash
- Up to two HyperRAM modules
Power
- User-selectable core and I/O voltages
- Powered from 5V USB
GateMateTM FPGA Series: Feature Summary by Device
The Cologne Chip GateMateTM family addresses a complete range of system requirements. The following table compares all available devices:
Device | Rel. size | Programmable Elements (CPE) 1) 2) |
Block RAM 3) | PLLs | SERDES | I/Os | Package | |||||
CPEs | 8-Inp-LUT trees | FF/Latches | 20Kb | 40Kb | single-ended | differential (LVDS) |
balls | size (mm) | ||||
CCGM1A1 | 1 | 20,480 | 20,480 | 40,960 | 64 | 32 | 4 | 1 | 162 | 81 | 324BGA | 15x15 |
CCGM1A2 | 2 | 40,960 | 40,960 | 81,920 | 128 | 64 | 8 | 2 | 162 | 81 | 324BGA | 15x15 |
CCGM1A4 | 4 | 81,920 | 81,920 | 163,840 | 256 | 128 | 16 | 4 | 154 | 77 | 324BGA | 15x15 |
CCGM1A9 | 9 | 184,320 | 184,320 | 368,640 | 576 | 288 | 36 | 9 | tba | tba | tba | tba |
CCGM1A16 | 16 | 327,680 | 327,680 | 655,360 | 1,024 | 512 | 64 | 16 | tba | tba | tba | tba |
CCGM1A25 | 25 | 512,000 | 512,000 | 1,024,000 | 1,600 | 800 | 100 | 25 | tba | tba | tba | tba |
1) CPEs have 2x4 or 8 inputs connected to a LUT tree 2) Each CPE can be used as 2x2 bit multiplier tile 3) Block RAM can have a max. data width of 20 either 40 Bits