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In this interview with Elektronik Praxis, Dr. Michael Gude, CEO of Cologne Chip, discusses the unique features of the new GateMate FPGA.

What sets GateMate apart from other FPGAs?

Dr. Gude highlights GateMate’s innovative architecture based on Cologne Programmable Elements (CPEs), which have eight inputs. This eliminates the need for cascading common gate circuits, resulting in faster operations compared to competitor products. The routing is simplified with six direct connections between neighboring elements, offering faster performance compared to slower multiplexer-based wiring. Additionally, only two PCB layers are required to manage all signal lines, simplifying board design.

How does GateMate handle different application demands without multiple FPGA families?

Gude explains that GateMate offers scalable performance through its patented manufacturing process. By adjusting the core voltage and clock frequency, the processing speed can be scaled by a factor of 2.5—dynamically during operation—essentially creating an “overdrive” mode for circuits. The FPGAs support three performance modes: Low-Power, Economy, and Speed, with core voltages of 0.9V, 1.0V, and 1.1V, respectively, allowing for versatile use in different applications.

Is there no need for speedgrade selection in production?

Cologne Chip avoids the typical speedgrade selection process, which complicates logistics and inventory. Instead, they offer a single chip that can be dynamically adjusted for different projects, from low-power to high-speed, improving flexibility for customers.

What’s special about the manufacturing process?

Cologne Chip uses a multi-die manufacturing technique, which allows them to produce FPGAs with different sizes from a single set of masks. Dies are interconnected on the wafer with over 1,000 lines per edge, making it possible to group them for larger FPGAs with multiple dies working together. This approach reduces costs and improves performance, particularly in terms of connection density, latency, and power consumption.

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This article from Elektronik Praxis introduces Cologne Chip’s GateMate FPGAs, developed in Cologne and competing against major players like Xilinx, Intel, Microchip, and Lattice. Known for their scalable architecture and unique Cologne Programmable Elements (CPEs), these FPGAs are produced in Dresden and promise low specific costs, making them highly competitive in the market. GateMate chips support a variety of performance modes and application areas, from IoT to AI and automation, while maintaining a low power footprint and ease of use in PCB design.

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This article from Markt & Technik highlights Cologne Chip’s entry into the FPGA market, a rare move for a German semiconductor company. Despite past failures by American firms, CEO Dr. Michael Gude believes the GateMate FPGA family has strong prospects for success. The family includes small to medium-complexity FPGAs suitable for a wide range of applications, from low-power to high-speed uses in industries like automotive, IoT, AI, and more. Key features include Cologne Programmable Elements (CPEs), JTAG, SerDes interfaces, and dual-port SRAM.

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This article from elektroniknet.de introduces Cologne Chip’s GateMate FPGA family, which offers small to medium-density components for a variety of applications like automation, communication, IoT, and more. GateMate stands out for its combination of logic density, low power consumption, and compact packaging, making it highly cost-effective. Designed and produced in Germany in collaboration with Globalfoundries, the chips benefit from European-based manufacturing, minimizing risks related to trade restrictions.

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