Here you find all relevant documentation for GateMate™ FPGA. The files are organised by topic, providing quick access to the information you need. Should you have any questions, please do not hesitate to contact us.
Please note: Data is subject to change without notice. Some of the information provided may be protected by patents or other rights.
Product Briefs
Datasheets
🆕 GateMate A1/A2 Datasheet
🗄️ GateMate A1/A2 Pin Lists
📄 Evaluation Board Datasheet
📄 Evaluation Board Schematics
📄 Programmer Datasheet
📄 Programmer Schematics
CAD Models
🔗 Official kicad-symbols and kicad-footprints
🗄️ Altium Designer Symbols and Footprint
📄 GateMate A1 BSDL File
User Guides
📄 Primitives Library
🗄️ Primitives Examples
🆕 Toolchain Guide
📄 GateMate A2 GPIO Bank Allocation Guide
📄 GateMate Integrated Logic Analyzer Handbook
Application Notes
📄 Interface Guide for 3.3V Signaling
IBIS Models
📄 rio25_zg_gpio_lvds_2d50v
📄 rio25_zg_gpio_lvds_1d80v
📄 rio25_zg_gpio_lvds_1d50v
📄 rio25_zg_gpio_lvds_1d20v
Packaging Regulations and Declarations
📄 REACH Declaration with 253 SVHC (2026)
📄 RoHS Declaration (2026)
📄 Packaging Regulations and Soldering Reflow Information